Description: Space-based computing has not kept up with the needs of current and future NASA missions. The objective of HPSC is to develop a next-generation flight computing system that addresses computational performance, energy management and fault tolerance needs of NASA missions through 2040 and beyond. HPSC offers a new flight computing architecture with the potential of 100X the computational capacity of current flight processors for the same amount of power, with provisions for extensibility and interoperability. HPSC is also a cross-cutting advance and technology multiplier, amplifying existing spacecraft capabilities and enabling new ones. Microchip’s HPSC SoC offering envisions the following key device features, capabilities, and benefits: • Integrates compute subsystems, memory controllers and peripheral interfaces • Compute cluster baseline from Microchip’s 2nd generation SoC design o Integrates multiple 64-bit RISC-V CPU cores for general application processing o Integrates a highly redundant system controller o Integrates optional dedicated cores for real-time applications o Compute complex is optimized for fault tolerant processing • Integrates hardware security o Encryption engine to support cryptographic applications o Root of trust for secure operations (secure boot, etc.) • Device subsystems are interconnected by an on-chip fabric • Multiple devices can be interconnected together for compute performance scale-out & fault tolerance • Integrates a wide range of low-speed and high-speed interfaces for connectivity to external peripherals • Process node: GlobalFoundries 12nm LP+ (to enable onshore manufacturing security) • Supports radiation tolerance necessary for space flight missions • Provides a complete software stack including toolchain and tools, system controller software, optimized Linux OS and a system-validated board support package (BSP) • Evaluation platform will be available to NASA to support software development and testing, and to enable the NASA Single Board Computer (SBC) development • Software reuse & portability between HPSC and Microchip FPGA product line

Benefits: HPSC is a NASA-led new flight computing architecture, which radically advances the capabilities of space-based computing.Enables significant capability advances in mission and science autonomy, intelligent vehicles, flagship science at discovery prices, crew assist, and much more.HPSC is a fault-tolerant 10-core RISC-V System-on-Chip (SoC) that offers extremely high performance per watt. HPSC will have a full defense grade security solution on chip 100X the computational capacity of current flight processors for the same amount of powerUnprecedented flexibility to trade among computational performance, energy management and fault toleranceHighly extensible; chiplets can be cascaded together and/or configured with specialized co-processorsHPSC will be fabricated on a DMEA “trusted" foundry – GlobalFoundries Fab 8 in Malta, New York Advances compute capabilities necessary for autonomy advancement Enables leverage of open source software ecosystems Enables more/better science returnScalable from small to large systemsEnables system resilience: in flight autonomy, adaptive behaviors:AI/MLEfficient and flexible architecture based on modular open and vibrant industry standards