This project will develop a Domain Specific Language (DSL) approach to interpret requirements and map them to formal specifications and legacy formats; explore and enhance the connection of TuLiP and SCA; develop methods to ensure semantics of the synthesized FSM designs map into implementations; and demonstrate the proof-of-concept synthesis on controller example cases. The key innovations will be: synthesis of FSM's that ensures a given formal specification is met (i.e., correct-by-construction). Also, complete software synthesis - no manually developed code>

To improve and optimize the use of combined control synthesis algorithms and code generation techniques to produce FSW directly from formal specifications.